1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating redundancy memory cells.
2. Description of the Related Art
In a prior art semiconductor memory device such as a dynamic random access memory (DRAM) device or a static random access memory device (SRAM) device, a plurality of redundancy memory cells are incorporated thereinto. As a result, even if two or more defective memory cells are found, the device can be relieved by replacing such defective memory cells with the redundancy memory cells.
Generally, the prior art semiconductor memory device is constructed by aplurality of bus lines, a plurality of normal memory cell arrays, a plurality of normal data amplifiers for amplifying data read from the normal memory cell arrays, a plurality of redundancy memory cell arrays, a plurality of redundancy data amplifiers for amplifying data read from the redundancy memory cell arrays and a plurality of bus selectors are connected to the redundancy data amplifiers and the bus lines, so as to selectively connect the redundancy data amplifiers to the bus lines. That is, the normal data amplifiers are always directly connected to the respective bus lines. This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, since the large area of the bus selectors is provided only on the side of the redundancy memory cell arrays, the layout is not uniform so that the layout design becomes complex. In addition, since there is no bus selector on the side of the normal memory cell arrays, the speed of the read operation from the normal memory cell arrays is different from the speed of the read operation from the redundancy memory arrays.